Systems that include integrated circuit (IC) devices typically include decoupling capacitors (also known as bypass capacitors) as well. A typical decoupling capacitor is a capacitor coupled between the power and ground pins (i.e., terminals) of a packaged IC to reduce noise on the power system within the IC. While in some cases the IC itself includes some decoupling capacitance, the amount of capacitance required is such that one or more additional discrete decoupling capacitors are usually added external to the packaged device.
In the past, the location of these discrete decoupling capacitors was a less important issue. The switching frequency of a device was relatively low, e.g., in the range of hundreds of kHz (kilohertz) to tens of MHz (megahertz). The transient currents within the device were also relatively low. Hence, parasitic inductance in the printed circuit board (PCB) mountings was not an important consideration. For example, for an IC mounted in a medium-performance package, whether leaded or surface-mounted to the PCB, a 0.1 uF (microfarad) decoupling capacitor could typically be mounted on the PCB anywhere within a few inches of the packaged IC.
Many ICs now operate at clock frequencies in the hundreds of MHz. At these higher frequencies, transient currents are significantly higher than in the past, and parasitic inductance is a much more important issue. Parasitic inductance within the capacitors themselves has been reduced by improving the packaging of the capacitors, e.g., by using only surface-mount packages and by reducing the size of the packages. (Smaller packages inherently have a lower parasitic inductance.) Parasitic inductance within the PCB mountings has also been reduced through improved layout techniques, e.g., by using dedicated power planes in the PCB, by improving capacitor land geometries, and by careful placement of the capacitors to reduce the distance between the packaged IC and the capacitors.
However, as operating frequencies continue to increase, even these measures become inadequate. One bottleneck in the current path between a decoupling capacitor and the associated packaged IC are the vias that transport charge from the capacitor lands through the PCB to the power planes, and then from the power planes through the PCB to the device. These vias can contribute parasitic inductance in the range of 1.5 nH (nanohenrys) each. If this via inductance could be reduced or eliminated, providing for high-frequency transient current would be much easier.
Therefore, it is desirable to provide systems and structures that provide decoupling capacitance to IC devices with reduced capacitor parasitic inductance. It is further desirable to reduce via parasitic inductance in these systems and structures.
In addition to the issues set forth above, an active circuit disposed on an integrated circuit die typically draws spikes of current from local power supply lines on the integrated circuit die. An active circuit, for example, can have a VCC power lead that is coupled to a VCC power terminal of the integrated circuit by a power supply line. Where the active circuit is disposed in the center of the integrated circuit die, the power supply line can be quite long.
If the long supply line has only a small resistance and inductance, then the active circuit can draw a spike of supply current through the supply line without a significant drop in the voltage on the VCC power lead of the active circuit. Where the active circuit is disposed in the center of the integrated circuit die, however, the long power supply line can have significant resistance and inductance. Accordingly, the voltage on the VCC power lead of the active circuit drops momentarily when the active circuit draws a spike of current and results in undesirable consequences. Due to the drop in the voltage on the VCC power lead, the active circuit may be momentarily unable to output a digital logic high voltage.
One technique used to prevent such undesirable dips in supply voltage is to provide a bypass capacitor close to the active circuit. When the active circuit draws a spike of supply current, much of this supply current is supplied by the local bypass capacitor, thereby reducing the magnitude of the current spike pulled through the VCC power supply line. By reducing the magnitude of the current spike pulled through the supply line, the magnitude of the associated voltage drop at the VCC power lead of the active device is reduced as well. See, for example, U.S. Pat. No. 6,144,225, entitled “Programmable Integrated Circuit Having Metal Plate Capacitors That Provide Local Switching Energy.” The need for bypass capacitance is recognized before a circuit is laid out, and extra bypass capacitance is designed into the integrated circuit.
Unfortunately, power supply problems in certain applications of an integrated circuit are often not properly anticipated during the design stage of the integrated circuit. An integrated circuit design may already be in use in a particular application in the field when problems are first detected and appreciated. Refabricating an integrated circuit is generally a very expensive process. Adding bypass capacitance by redesigning and laying out the integrated circuit can be exceedingly expensive and slow. A less expensive and faster way of providing local bypass capacitance is desired.
In addition to the problem of having to provide bypass capacitance for an already-designed integrated circuit, there also sometimes exists a problem where the interconnections between the terminals on the integrated circuit and signal traces on the printed circuit are to be changed. The printed circuit board may be designed incorrectly such that traces on the printed circuit board are coupled to the wrong integrated circuit package terminals. It would be desirable to be able to correct for this problem without having to redesign and refabricate the printed circuit.
In addition to the bypass capacitance and signal redistribution problems set forth above, problems with impedance mismatch sometimes exist. For example, where the output impedance of a driving circuit on an integrated circuit differs significantly from a characteristic impedance of a signal line onto which the driving circuit drives a signal, undesirable reflections may be generated. The signal line may, for example, be a signal line on a printed circuit board, where the integrated circuit is a packaged integrated circuit disposed on the printed circuit board. Similar undesirable reflections may also be generated where the input impedance of a receiving circuit on the integrated circuit differs significantly from a characteristic impedance of a signal line through which the signal is supplied to the receiving circuit. Although termination resistors can sometimes be provided to match input and output impedances to signal line impedances, there is sometimes not enough physical space on the printed circuit board to accommodate additional discrete components close to the integrated circuit. Even if there is enough physical space to provide such additional components adequately close to the integrated circuit, doing so involves refabricating the printed circuit board to provide solder pads to which the additional discrete components can be attached. A solution to such impedance mismatch problems is desired that overcomes the space problem and that does not involve refabricating the printed circuit board.